A memory, in particular, a static random access memory (SRAM), is configured to operate in retention till access (RTA) mode to reduce active array leakage by keeping the array supply at a diode voltage level below the supply voltage. In general, an SRAM is divided into blocks of 32 rows or 16 rows. When operating, a switch is used to bring a voltage of a block being accessed in the SRAM, to the full voltage. In order to support the high memory performance, the size of the switch needs to be significantly high. This results in high switch area and high peak current. Further, large on die decoupling capacitance is needed to support high peak current which in turn increases the overall system on chip (SoC) area and leakage. As the peak current depends on the SRAM usage in the SoC, it becomes challenging to predict peak current in the system. This leads to conservative value of decoupling capacitance requirements.